RXCHFR=Val_0x0
Receive FIFO Flush Register 0
RXCHFR | Receive Channel FIFO Reset. Writing a 0x1 to this bit flushes the channel RX FIFO (this is a self clearing bit). The RX channel or block must be disabled prior to writing to this bit. 0 (Val_0x0): Does not flush the channel RX FIFO 1 (Val_0x1): Flushes the channel RX FIFO |